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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003, zarlink semiconductor inc. all rights reserved. features ? 16,384-channel x 16,384-channel non-blocking unidirectional switching.the backplane and local inputs and outputs can be combined to form a non-blocking switching matrix with 32 input streams and 32 output streams ? 8,192-channel x 8,192-channel non-blocking backplane input to local output stream switch ? 8,192-channel x 8,192-channel non-blocking local input to backplane output stream switch ? 8,192-channel x 8,192-channel non-blocking backplane input to backplane output switch ? 8,192-channel x 8,192-channel non-blocking local input to local output stream switch ? backplane port accepts 16 input and 16 output st-bus streams with data rate of 32.768mbps ? local port accepts 16 input and 16 output st- bus streams with data rate of 32.768mbps ? exceptional input clock jitter tolerance (14ns) ? per-stream bit delay for local and backplane input streams ? per-stream advancement for local and backplane output streams ? constant 2-frame throughput delay for frame integrity ? per-channel high impedance output control for local and backplane streams ? per-channel driven-high output control for local and backplane streams ? per-channel message mode for local and backplane output streams ? connection memory block programming for fast device initialization ? automatic selection between st-bus and gci- bus operation ? non-multiplexed motorola microprocessor interface november 2003 ordering information ZL50063gac 196-ball pbga -40 c to +85 c ZL50063 16k-channel digital switch with high jitter tolerance, single rate (32mbps), and 32 inputs and 32 output data sheet figure 1 - ZL50063 functional block diagram backplane data memories (4,096 channels) ds cs r/w a14-0 dta d15-0 test port microprocessor interface and internal registers v ss (gnd) v dd_core tdi tdo tck trst tms lsto0-15 (4,096 locations) reset local interface connection memory bsti0-15 input timing unit fp8i pll lsti0-15 interface backplane bsto0-15 local c8i v dd_io ode c8o c16o fp8o fp16o v dd_pll output timing unit (4,096 locations) connection memory backplane interface local local data memories (4,096 channels) bors lors
ZL50063 data sheet 2 zarlink semiconductor inc. ? conforms to the mandatory requirements of the ieee-1149.1 (jtag) standard ? memory built-in-self-test (bist), controlled via microprocessor register ? 1.8v core supply voltage ? 3.3v i/o supply voltage ? 5v tolerant inputs, outputs and i/os applications ? central office switches (class 5) ? media gateways ? class-independent switches ? access concentrators ? scalable tdm-based architectures ? digital loop carriers
ZL50063 data sheet 3 zarlink semiconductor inc. device overview the ZL50063 has two data ports, the backplane and the local port. both the backplane and local ports operate at 32.768mbps. the ZL50063 contains two data memory blocks (backplane and local) to provide the following switching path configurations: ? input-to-output unidirectional, supporting 16k x 16k switching ? backplane-to-local bi-directional, supporting 8k x 8k data switching, ? local-to-backplane bi-directional, supporting 8k x 8k data switching, ? backplane-to-backplane bi-directional, supporting 8k x 8k data switching. ? local-to-local bi-directional, supporting 8k x 8k data switching. the device contains two connection memory blocks, one for the backplane output and one for the local output. data to be output on the serial streams may come from either of the data memories (connection mode) or directly from the connection memory contents (message mode). in connection mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (stored in data memory) to be switched. in message mode, microprocessor data can be written to the connection memory for broadcast on the output streams on a per channel basis. this feature is useful for transferring control and status information to external circuits or other st-bus devices. the device uses a master frame pulse (fp8i ) and master clock (c8i ) to define the input frame boundary and timing for both the backplane port and the local port. the device will automatically detect whether an st-bus or a gci- bus style frame pulse is being used. there is a two-frame delay from the time reset is de-asserted to the establishment of full switch functionality. during this period, the input frame pulse format is determined before switching begins. the device provides fp8o , fp16o , c8o and c16o outputs to support external devices connected to the outputs of the backplane and local ports. a non-multiplexed motorola microprocessor port allows programming of the various device operation modes and switching configurations. the microprocessor port provides access for register read/write, connection memory read/write and data memory read-only operations. the port has a 15-bit address bus, 16-bit data bus and 4 control signals. the microprocessor may monitor channel data in the backplane and local data memories. the mandatory requirements of the ieee-1149.1 (jtag) standard are fully supported via a dedicated test port. the ZL50063 is available in one package: ? a 15mm x 15mm body, 1mm ball-pitch, 196-pbga.
ZL50063 data sheet table of contents 4 zarlink semiconductor inc. 1.0 unidirectional and bi-directional switching applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.1 flexible configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.1.1 non-blocking unidirectional configuration (typical system configuration) . . . . . . . . . . . . . . . . . . 15 1.1.2 non-blocking bi-directional configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.1.3 blocking bi-directional configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 switching configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.1 unidirectional switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.2 backplane-to-local path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.3 local-to-backplane path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.4 backplane-to-backplane path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.5 local-to-local path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.6 port operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.6.1 local output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.6.2 backplane output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 frame pulse input and master input clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 input frame pulse and generated frame pulse alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 jitter tolerance improvement circuit - frame boundary discriminator. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 input clock jitter tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.0 input and output offset programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 input offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.1 input bit delay programming (backplane and local input streams) . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 output advancement programming (backplane and local output streams) . . . . . . . . . . . . . . . . . . . . . . 21 4.0 port high-impedance control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.0 data delay through the switching paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.0 microprocessor port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.0 device power-up, initialization and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.0 connection memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1 local connection memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2 backplane connection memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.3 connection memory block programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.3.1 memory block programming procedure: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.0 memory built-in-self-test (bist) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.0 jtag port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.1 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.2 tap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2.1 test instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2.2 test data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2.2.3 the device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.3 boundary scan description language (bsdl) file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.0 memory address mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.1 local data memory bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.2 backplane data memory bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.3 local connection memory bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.4 backplane connection memory bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12.0 internal register mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 13.0 detailed register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ZL50063 data sheet table of contents 5 zarlink semiconductor inc. 13.1 control register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 13.2 block programming register (bpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13.3 local input bit delay registers (lidr0 to lidr15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 13.3.1 local input delay bits 4-0 (lid[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 13.4 backplane input bit delay registers (bidr0 to bidr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13.4.1 backplane input delay bits 4-0 (bid[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13.5 local output advancement registers (loar0 to loar15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 13.5.1 local output advancement bits 1-0 (loa1-loa0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 13.6 backplane output advancement registers (boar0 - boar15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.6.1 backplane output advancement bits 1-0 (boa1-boa0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.7 memory bist register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.8 device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.0 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15.0 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ZL50063 data sheet list of figures 6 zarlink semiconductor inc. figure 1 - ZL50063 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - ZL50063 pbga connections (196 pbga, 15mm x 15mm) pin diagram (as viewed through top of package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3 - 16,384 x 16,384 channels (32mbps), unidirectional switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4 - 8,192 x 8,192 channels (32mbps), bi-directional switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5 - 12,288 by 4,096 channels blocking bi-directional configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6 - st-bus and gci-bus input timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7 - input and output (generated) frame pulse alignment for different data rates . . . . . . . . . . . . . . . . . 18 figure 8 - backplane and local input bit delay timing diagram for data rate of 32mbps. . . . . . . . . . . . . . . . . . 20 figure 9 - backplane and local input bit delay or sampling point selection timing diagram for data rate of 32mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10 - local and backplane output advancement timing diagram for data rate of 32mbps . . . . . . . . . . . 22 figure 11 - data throughput delay with input ch0 switched to output ch0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12 - data throughput delay with input ch0 switched to output ch13. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13 - data throughput delay with input ch13 switched to output ch0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14 - hardware reset de-assertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15 - frame boundary conditions, st-bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 16 - frame boundary conditions, gci-bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 17 - input and output clock timing diagram for st-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 18 - input and output clock timing diagram for gci-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 19 - st-bus local/backplane data timing diagram (32mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 20 - gci-bus local/backplane data timing diagram (32mbps). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 21 - serial output and external control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 22 - output driver enable (ode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 23 - motorola non-multiplexed bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 24 - jtag test port timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
ZL50063 data sheet list of tables 7 zarlink semiconductor inc. table 1 - local and backplane output enable control priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 2 - local and backplane connection memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 3 - local connection memory in block programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 4 - backplane connection memory in block programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5 - address map for data and connection memory locations (a14 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 table 6 - local data memory (ldm) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7 - backplane data memory (bdm) bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8 - lcm bits for source-to-local switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9 - bcm bits for source-to-backplane switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10 - address map for registers (a14 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 11 - control register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12 - block programming register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 13 - local input bit delay register (lidrn) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14 - local input bit delay and sampling point programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 15 - backplane input bit delay register (bidrn) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 16 - backplane input bit delay and sampling point programming table. . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 17 - local output advancement register (loar) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 18 - local output advancement (loar) programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 19 - backplane output advancement register (boar) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 20 - backplane output advancement (boar) programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 table 21 - memory bist register (mbistr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 22 - device identification register (dir) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
ZL50063 data sheet 8 zarlink semiconductor inc. figure 2 - ZL50063 pbga connections (196 pbga, 15mm x 15mm) pin diagram (as viewed through top of package) pinout diagram: (as viewed through top of package) a1 corner identified by metallized marking, mold indent, ink dot, or right-angled corner. 1234567891011121314 absto1bsto2a4a5a8a9a12a13r/w cs tms tdo ic_ open trst b a0bsto5bsto0a1a2a7a11a14odetditckic_ open lsto0 lsto1 c ic_gnd bsto7 bsto8 bsto3 bsto4 a6 a10 ds reset ic_ open ic_gnd ic_ open ic_gnd lsto3 d ic_gnd bsto6 bsto10 gnd a3 vdd_io vdd_io vdd_io dta vdd_io gnd lsto4 lsto6 lsto2 e bsto12 bsto11 bsto13 vdd_io gnd vdd_ core vdd_ core vdd_ core vdd_ core gnd vdd_io lsto8 lsto7 lsto5 f bsto9 bsto14 bsto15 vdd_io vdd_ core gnd gnd gnd gnd vdd_ core vdd_io lsto12 lsto13 lsto9 g bsti0 bors vdd_ core vdd_io vdd_ core gnd gnd gnd gnd vdd_ core vdd_io lsto11 lsto15 lsto10 h bsti1 bsti2 bsti3 vdd_io vdd_ core gnd gnd gnd gnd vdd_ core vdd_io vdd_ core lors lsto14 j bsti4 bsti5 bsti7 vdd_io vdd_ core gnd gnd gnd gnd vdd_ core vdd_io lsti5 lsti1 lsti2 k bsti6 bsti9 bsti13 vdd_io gnd vdd_ core vdd_ core vdd_ core vdd_ core gnd vdd_io lsti15 lsti3 lsti0 l bsti8 bsti11 bsti14 gnd vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io gnd lsti14 lsti8 lsti6 m bsti10 bsti15 d15 d14 d12 d5 ic_gnd ic_gnd c16o fp8i lsti13 lsti10 lsti7 lsti4 n bsti12 d13 d10 d11 d7 d3 d0 ic_gnd vdd_ pll c8o fp8o lsti11 lsti12 lsti9 p gnd d9 d8 d6 d4 d2 d1 ic_gnd ic_ open c8i ic_ open fp16o gnd gnd
ZL50063 data sheet 9 zarlink semiconductor inc. pin description pin name ZL50063 package coordinates (196-ball pbga) description device timing c8i p10 master clock (5v tolerant schmitt-triggered input). this pin accepts an 8.192mhz clock. the internal frame boundary is aligned with the clock falling or rising edge, as controlled by the c8ipol bit in the control register. input data on both the backplane and local sides (bsti0-15 and lsti0-15) must be aligned to this clock and the accompanying input frame pulse, fp8i . fp8i m10 frame pulse input (5v tolerant schmitt-triggered input) . when the frame pulse width bit (fpw) of the control register is low (default), this pin accepts a 122ns-wide frame pulse. when the fpw bit is high, this pin accepts a 244ns-wide frame pulse. the device will automatically detect whether an st-bus or gci-bus style frame pulse is applied. input data on both the backplane and local sides (bsti0-15 and lsti0-15) must be aligned to this frame pulse and the accompanying input clock, c8i . c8o n10 c8o output clock (5v tolerant three-state output). this pin outputs an 8.192mhz clock generated within the device. the clock falling edge or rising edge is aligned with the output frame boundary presented on fp8o ; this edge polarity alignment is controlled by the copol bit of the control register. output data on both the backplane and local sides (bsto0-15 and lsto0-15) will be aligned to this clock and the accompanying output frame pulse, fp8o . fp8o n11 frame pulse output (5v tolerant three-state output). when the frame pulse width bit (fpw) of the control register is low (default), this pin outputs a 122ns-wide frame pulse. when the fpw bit is high, this pin outputs a 244ns-wide frame pulse. the frame pulse, running at 8khz rate, will have the same format (st-bus or gci-bus) as the input frame pulse (fp8i ). output data on both the backplane and local sides (bsto0-15 and lsto0-15) will be aligned to this frame pulse and the accompanying output clock, c8o . c16o m9 c16o output clock (5v tolerant three-state output). this pin outputs a 16.384mhz clock generated within the device. the clock falling edge or rising edge is aligned with the output frame boundary presented on fp16o ; this edge polarity alignment is controlled by the copol bit of the control register. output data on both the backplane and local sides (bsto0-15 and lsto0-15) will be aligned to this clock and the accompanying output frame pulse, fp16o . fp16o p12 frame pulse output (5v tolerant three-state output). when the frame pulse width bit (fpw) of the control register is low (default), this pin outputs a 61ns-wide frame pulse. when the fpw bit is high, this pin outputs a 122ns-wide frame pulse. the frame pulse, running at 8khz rate, will have the same format (st-bus or gci-bus) as the input frame pulse (fp8i ). output data on both the backplane and local sides (bsto0-15 and lsto0-15) will be aligned to this frame pulse and the accompanying output clock, c16o .
ZL50063 data sheet 10 zarlink semiconductor inc. backplane and local inputs bsti0-7 g1, h1, h2, h3, j1, j2, k1, j3 backplane serial input streams 0 to 7 (5v tolerant inputs with internal pull-downs). these pins accept serial tdm data streams at a fixed data rate of 32.768mbps (with 512 channels per stream). bsti8-15 l1, k2, m1, l2, n1, k3, l3, m2 backplane serial input streams 8 to 15 (5v tolerant inputs with internal pull-downs). these pins accept serial tdm data streams at a fixed data rate of 32.768mbps (with 512 channels per stream). lsti0-7 k14, j13, j14, k13, m14, j12, l14, m13 local serial input streams 0 to 7 (5v tolerant inputs with internal pull-downs). these pins accept serial tdm data streams at a fixed data rate of 32.768mbps (with 512 channels per stream). lsti8-15 l13, n14, m12, n12, n13, m11, l12, k12 local serial input streams 8 to 15 (5v tolerant inputs with internal pull-downs). these pins accept serial tdm data streams at a fixed data rate of 32.768mbps (with 512 channels per stream). backplane and local outputs and control ode b9 output drive enable (5v tolerant input with internal pull-up) . an asynchronous input providing output enable control to the bsto0-15 and lsto0-15 outputs. when low, the bsto0-15 and lsto0-15 outputs are driven high or high impedance (dependent on the bors and lors pin settings respectively). when high, the outputs bsto0-15 and lsto0-15 are enabled. bors g2 backplane output reset state (5v tolerant input with internal pull-down) . when this input is low, the device will initialize with the bsto0-15 outputs driven high. following initialization, the backplane stream outputs are always active. when this input is high, the device will initialize with the bsto0-15 outputs at high impedance. following initialization, the backplane stream outputs may be set active or high impedance using the ode pin or on a per-channel basis with the be bit in the backplane connection memory. bsto0-7 b3, a1, a2, c4, c5, b2, d2, c2 backplane serial output streams 0 to 7 (5v tolerant, three-state outputs with slew-rate control). these pins output serial tdm data streams at a fixed data rate of 32.768mbps (with 512 channels per stream). refer to the descriptions of the bors and ode pins for control of the output high or high impedance state. pin description (continued) pin name ZL50063 package coordinates (196-ball pbga) description
ZL50063 data sheet 11 zarlink semiconductor inc. bsto8-15 c3, f1, d3, e2, e1, e3, f2, f3 backplane serial output streams 8 to 15 (5v tolerant, three-state outputs with slew-rate control). these pins output serial tdm data streams at a fixed data rate of 32.768mbps (with 512 channels per stream). refer to the descriptions of the bors and ode pins for control of the output high or high impedance state. lors h13 local output reset state (5v tolerant input with internal pull-down) . when this input is low, the device will initialize with the lsto0-15 outputs driven high. following initialization, the local stream outputs are always active. when this input is high, the device will initialize with the lsto0-15 outputs at high impedance. following initialization, the local stream outputs may be set active or high impedance using the ode pin or on a per-channel basis with the le bit in the local connection memory. lsto0-7 b13, b14, d14, c14, d12, e14, d13, e13 local serial output streams 0 to 7 (5v tolerant three-state outputs with slew-rate control). these pins output serial tdm data streams at a fixed data rate of 32.768mbps (with 512 channels per stream). refer to the descriptions of the lors and ode pins for control of the output high or high impedance state. lsto8-15 e12, f14, g14, g12, f12, f13, h14, g13 local serial output streams 8 to 15 (5v tolerant three-state outputs with slew-rate control). these pins output serial tdm data streams at a fixed data rate of 32.768mbps (with 512 channels per stream). refer to the descriptions of the lors and ode pins for control of the output high or high impedance state. microprocessor port signals a0 - a14 b1, b4, b5, d5, a3, a4, c6, b6, a5, a6, c7, b7, a7, a8, b8 address 0 - 14 (5v tolerant inputs). these pins form the 15-bit address bus to the internal memories and registers. a0 = lsb d0 - d15 n7, p7, p6, n6, p5, m6, p4, n5, p3, p2, n3, n4, m5, n2, m4, m3 data bus 0 - 15 (5v tolerant inputs/outputs with slew-rate control). these pins form the 16-bit data bus of the microprocessor port. d0 = lsb cs a10 chip select (5v tolerant input). active low input used by the microprocessor to enable the microprocessor port access. note that a minimum of 30ns must separate the de-assertion of dta (to high) and the assertion of cs and/or ds to initiate the next access. pin description (continued) pin name ZL50063 package coordinates (196-ball pbga) description
ZL50063 data sheet 12 zarlink semiconductor inc. ds c8 data strobe (5v tolerant input). this active low input works in conjunction with cs to enable the microprocessor port read and write operations. note that a minimum of 30ns must separate the de-assertion of dta (to high) and the assertion of cs and/or ds to initiate the next access. r/w a9 read/write (5v tolerant input). this input controls the direction of the data bus lines (d0-d15) during a microprocessor access. dta d9 data transfer acknowledgment (5v tolerant three-state output). this active low output indicates that a data bus transfer is complete. a pull-up resistor is required to hold a high level. note that a minimum of 30ns must separate the de-assertion of dta (to high) and the assertion of cs and/or ds to initiate the next access. reset c9 device reset (5v tolerant input with internal pull-up). this input (active low) asynchronously applies reset and synchronously releases reset to the device. in the reset state, the outputs lsto0-15 and bsto0-15 are set to a high or high impedance state, depending on the state of the lors and bors external control pins, respectively. the assertion of this pin also clears the device registers and internal counters. refer to section 7.3 on page 25 for the timing requirements regarding this reset signal . jtag control signals tck b11 test clock (5v tolerant input). provides the clock to the jtag test logic. tms a11 test mode select (5v tolerant input with internal pull-up). jtag signal that controls the state transitions of the tap controller. tdi b10 test serial data in (5v tolerant input with internal pull-up). jtag serial test instructions and data are shifted in on this pin. tdo a12 test serial data out (5v tolerant three-state output). jtag serial data is output on this pin on the falling edge of tck. this pin is held in a high impedance state when jtag is not enabled. trst a14 test reset (5v tolerant input with internal pull-up). asynchronously initializes the jtag tap controller to the test-logic-reset state. this pin must be pulsed low during power-up for jtag testing. this pin must be held low for normal functional operation of the device. pin description (continued) pin name ZL50063 package coordinates (196-ball pbga) description
ZL50063 data sheet 13 zarlink semiconductor inc. power and ground pins v dd_io d6, d7, d8, d10, e4, e11, f4, f11, g4, g11, h4, h11, j4, j11, k4, k11, l5, l6, l7, l8, l9, l10 power supply for periphery circuits: +3.3v v dd_core e6, e7, e8, e9, f5, f10, g3, g5, g10, h5, h10, h12, j5, j10, k6, k7, k8, k9 power supply for core circuits: +1.8v v dd_pll n9 power supply for analog pll: +1.8v v ss (gnd) d4, d11, e5, e10, f6, f7, f8, f9, g6, g7, g8, g9, h6, h7, h8, h9, j6, j7, j8, j9, k5, k10, l4, l11, p1, p13, p14 ground. unused pins ic_open a13, b12, c10, c12, p9, p11 internal connections - open. these pins must be left unconnected. ic_gnd c1, c11, c13, d1, m7, m8, n8, p8 internal connections - gnd. these pins must be tied low. pin description (continued) pin name ZL50063 package coordinates (196-ball pbga) description
ZL50063 data sheet 14 zarlink semiconductor inc. 1.0 unidirectional and bi-directional switching applications the ZL50063 has a maximum capacity of 16,384 input channels and 16,384 output channels. this is calculated from the number of streams and channels: 32 input streams (16 backplane, 16 local) at 32.768mbps and 32 output streams (16 backplane, 16 local) at 32.768mbps, with each stream providing 512 channels. a typical mode of operation is to separate the input and output streams to form a unidirectional switch, as shown in figure 3 below. figure 3 - 16,384 x 16,384 channels (32mbps), unidirectional switching in this system, the backplane and local input streams are combined, and the backplane and local output streams are combined, so that the switch appears as a 32 input stream by 32 output stream switch. this gives the maximum 16,384 x 16,384 channel capacity. often a system design needs to differentiate between a backplane and a local side, or it needs to put the switch in a bi-directional configuration. in this case, the ZL50063 can be used as shown in figure 4 to give 8,192 x 8,192 channel bi-directional capacity. figure 4 - 8,192 x 8,192 channels (32mbps), bi-directional switching in this system setup, the chip has a capacity of 8,192 input channels and 8,192 output channels on the backplane side, as well as 8,192 input channels and 8,192 output channels on the local side. note that some or all of the output channels on one side can come from the other side, e.g., backplane input to local output switching. 1.1 flexible configuration the ZL50063 can be configured as an 16k by 16k non-blocking unidirectional digital switch, a 8k by 8k non-blocking bi-directional digital switch, or as a blocking switch with various switching capacities. ZL50063 16 streams 16 streams 16 streams 16 streams bsti0-15 lsti0-15 bsto0-15 lsto0-15 input output ZL50063 16 streams 16 streams 16 streams 16 streams bsti0-15 bsto0-15 lsto0-15 lsti0-15 backplane local
ZL50063 data sheet 15 zarlink semiconductor inc. 1.1.1 non-blocking unidirectional configuration (typical system configuration) because the input and output drivers are synchronous, the user can combine input backplane streams and input local streams as well as output backplane streams and output local streams to increase the total number of input and output streams of the switch in a unidirectional configuration, as shown in figure 3. ? 16,384-channel x 16,384-channel non-blocking switching from input to output streams 1.1.2 non-blocking bi-directional configuration another typical application is to configure the ZL50063 as a non-blocking 8k by 8k bi-directional switch, as shown in figure 4: ? 8,192-channel x 8,192-channel non-blocking switching from backplane input to local output streams ? 8,192-channel x 8,192-channel non-blocking switching from local input to backplane output streams ? 8,192-channel x 8,192-channel non-blocking switching from backplane input to backplane output streams ? 8,192-channel x 8,192-channel non-blocking switching from local input to local output streams 1.1.3 blocking bi-directional configuration the ZL50063 can be configured as a blocking bi-directional switch if it is an application requirement. for example, it can be configured as a 12k by 4k bi-directional blocking switch, as shown in figure 5: ? 12,288-channel x 4,096-channel blocking switching from backplane input to local output streams ? 4,096-channel x 12,288-channel blocking switching from local input to backplane output streams ? 12,288-channel x 12,288-channel non-blocking switching from backplane input to backplane output streams ? 4,096-channel x 4,096-channel non-blocking switching from local input to local output streams figure 5 - 12,288 by 4,096 channels blocking bi-directional configuration ZL50063 12k by 12k lsto8-15 lsti8-15 4k by 4k lsti0-7 bsti0-15 bsto0-15 lsto0-7 12k by 4k 4k by 12k total 8 streams input and 8 streams output total 24 streams input and 24 streams output
ZL50063 data sheet 16 zarlink semiconductor inc. 2.0 functional description 2.1 switching configuration the device supports five switching configurations: (1) unidirectional switch, (2) backplane-to-local, (3) local-to-backplane, (4) backplane-to-backplane, and (5) local-to-local. the following sections describe the switching paths in detail. configurations (2) - (5) enable a non-blocking bi-directional switch with 8,192 backplane input/output channels at backplane stream data rates of 32.768mbps, and 8,192 local input/output channels at local stream data rates of 32.768mbps. the switching paths of configurations (2) to (5) may be operated simultaneously. 2.1.1 unidirectional switch the device can be configured as a 16,384 x 16,384 unidirectional switch by grouping together all input streams and all output streams. all streams operate at a data rate of 32.768mbps. 2.1.2 backplane-to-local path the device can provide data switching between the backplane input port and the local output port. the local connection memory determines the switching configurations. 2.1.3 local-to-backplane path the device can provide data switching between the local input port and the backplane output port. the backplane connection memory determines the switching configurations. 2.1.4 backplane-to-backplane path the device can provide data switching between the backplane input and output ports. the backplane connection memory determines the switching configurations. 2.1.5 local-to-local path the device can provide data switching between the local input and output ports. the local connection memory determines the switching configurations. 2.1.6 port operation the local port has 16 input (lsti0-15) and 16 output (lsto0-15) data streams. similarly, the backplane port has 16 input (bsti0-15) and 16 output (bsto0-15) data streams. all the streams operate at 32.768mbps. the timing of the input and output clocks and frame pulses is shown in figure 7, ?input and output (generated) frame pulse alignment for different data rates? on page 18. the input traffic are aligned based on the fp8i and c8i input timing signals, while the output traffic are aligned based on the fp8o and c8o output timing signals. 2.1.6.1 local output port operation of stream data in connection mode or message mode is determined by the state of the lmm bit of the local connection memory. the channel high impedance state is controlled by the le bit of the local connection memory. the data source (i.e. from the local or backplane data memory) is determined by the lsrc bit of the local connection memory. refer to section 8.1, local connection memory, and section 11.3, local connection memory bit definition for more details.
ZL50063 data sheet 17 zarlink semiconductor inc. 2.1.6.2 backplane output port operation of stream data in connection mode or message mode is determined by the state of the bmm bit of the backplane connection memory and the channel high impedance state is controlled by the be bit of the backplane connection memory. the data source (i.e. from the local or backplane data memory) is determined by the bsrc bit of the backplane connection memory. refer to section 8.2, backplane connection memory and section 11.4, backplane connection memory bit definition for more details. 2.2 frame pulse input and master input clock timing the input frame pulse (fp8i ) is an 8khz input signal active for 122ns or 244ns at the frame boundary. the fpw bit in the control register must be set according to the applied pulse width. see pin description and table 11, ?control register bits? on page 32, for details. the active state and timing of fp8i can conform either to the st-bus or to the gci-bus as shown in figure 6, st-bus and gci-bus input timing diagram. the ZL50063 device will automatically detect whether an st-bus or a gci-bus style frame pulse is being used for the master frame pulse (fp8i ). the output frame pulses (fp8o and fp16o ) are always of the same style (st-bus or gci-bus) as the input frame pulse. the active edge of the input clock (c8i) shall be selected by the state of the control register bit c8ipol. note that the active edge of st-bus is falling edge, which is the default mode of the device, while gci-bus uses rising edge as the active edge. although gci frame pulse will be automatically detected, to fully conform to gci-bus operation, the device should be set to use c8i rising edge as the active edge (by setting bit c8ipol high) when gci-bus is used. for the purposes of describing the device operation, the remaining part of this document assumes the st-bus frame pulse format with a single width frame pulse of 122ns and a falling active clock-edge, unless explicitly stated otherwise. in addition, the device provides fp8o , fp16o , c8o and c16o outputs to support external devices which connect to the output ports. the generated frame pulses (fp8o , fp16o ) will be provided in the same format as the master frame pulse (fp8i ). the polarity of c8o and c16o , at the frame boundary, can be controlled by the control register bit, copol. an analog phase lock loop (apll) is used to multiply the input clock frequency on c8i to generate an internal clock signal operating at 131.072mhz. figure 6 - st-bus and gci-bus input timing diagram fp8i (st-bus) (8.192mhz) channel 255 channel 0 c8i (gci-bus) (8khz) (8khz) fp8i (gci-bus) 7 2 3 4 5 6 10 bsti/lsti0-15 (32mbps) st-bus channel 0 72 3 4 5 610 channel 1 2 310 7 2 3 4 5 6 10 channel 511 2 3 4 5 610 channel 510 76 (8.192mhz) c8i (st-bus) 0 5 4 3 2 1 67 bsti/lsti0-15 (32mbps) gci-bus channel 0 05 4 3 2 167 channel 1 5 467 05 4 3 2 167 channel 511 5 4 3 2 167 channel 510 01
ZL50063 data sheet 18 zarlink semiconductor inc. 2.3 input frame pulse and generated frame pulse alignment the ZL50063 accepts a frame pulse (fp8i ) and generates two frame pulse outputs, fp8o and fp16o , which are aligned to the master frame pulse. there is a constant throughput delay for data being switched from the input to the output of the device such that data which is input during frame n is output during frame n+2. for further details of frame pulse conditions and options, see section 13.1, control register (cr), figure 15, frame boundary conditions, st-bus operation, and figure 16, frame boundary conditions, gci-bus operation. figure 7 - input and output (generated) frame pulse alignment for different data rates the t fbos is the offset between the input frame pulse, fp8i , and the generated output frame pulse, fp8o . refer to the ?ac electrical characteristics,? on page 47. note that although the figure above shows the traditional setups of the frame pulses and clocks for both st-bus and gci-bus configurations, the devices can be configured to accept/generate double-width frame pulses (if the fpw bit in the control register is set) as well as to use the opposite clock edge for frame-boundary determination (using the c8ipol and copol bits in the control register). see the timing diagrams in ?ac electrical characteristics,? on page 47 for all of the available configurations. 2.4 jitter tolerance improvement circuit - frame boundary discriminator to improve the jitter tolerance of the ZL50063, a frame boundary discriminator (fbd) circuit was added to the device. this circuit is enabled by setting the control register bit fbden to high. by default the fbd is disabled. the fbd can operate in two modes, as controlled by the fbd_mode[2:0] bits of the control register. when bits fbd_mode[2:0] are set to 000 b , the fbd is set to handle lower frequency jitter only (<8khz). when bits fbd_mode[2:0] are set to 111 b , the fbd can handle both low frequency and high frequency jitter. all other values are reserved. these bits are ignored when bit fbden is low. it is strongly recommended that if bit fbden is set high, bits fbd_mode[2:0] should be set to 111 b to improve the high frequency jitter handling capability. to achieve the best jitter tolerance performance, it is also recommended that the input data sampling point be optimized. in most applications, the optimum sampling point is 1/2 instead of the default 3/4 (it can be changed by programming all the lidr and bidr registers). this will give more allowance for sampling point variations caused by jitter. there are, however, some cases where data experience more delay than the timing signals. a common example is when multiple data lines are tied together to form bidirectional buses. the large bus loading may cause data to be delayed. if this is the case, the optimum sampling point may be 3/4 or 4/4 instead of 1/2. the optimum sampling point is dependent on the application. the user should optimize the sampling point to achieve the best jitter tolerance performance. c8o fp8o fp8i c8i t fbos bsto/lsto0- 15 (32mbps) ch 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 21222324252627282930313233 3435 363738394041 424344 454647 bsti/lsti 0-15 (32mbps) ch 0 1 2 3 4 5 6 7 8 9 10 1112131415161718 1920 212223 24252627282930313233 3435363738394041 424344454647
ZL50063 data sheet 19 zarlink semiconductor inc. 2.5 input clock jitter tolerance jitter tolerance can not be accurately represented by just one number. jitter of the same amplitude but different frequency spectrum can have different effect on the operation of a device. for example, a device that can tolerate 20ns of jitter of 10khz frequency may only be able to tolerate 10ns of jitter of 1mhz frequency. therefore, jitter tolerance should be represented as a spectrum over frequency. the highest possible jitter frequency is half of the carrier frequency. in the case of the ZL50063, the input clock is 8.192mhz, and the jitter associated with this clock can have the highest frequency component at 4.096mhz. for the above reasons, jitter tolerance of the ZL50063 has been characterized at 32.768mbps. tolerance of jitter of different frequencies are shown in the ?ac electrical characteristics? section, table ?input clock jitter tolerance? on page 55. the jitter tolerance improvement circuit was enabled (control register, bit fbden set high, and bits fbd_mode[2:0] set to 111 b ), and the sampling point was optimized. 3.0 input and output offset programming various registers are used to control the input sampling point (delay) and the output advancement for the local and backplane streams. the following sections explain the details of these offset programming features. 3.1 input offsets control of the input bit delay allows each input stream to have a different frame boundary with respect to the master frame pulse, fp8i . each input stream can be individually delayed by up to 7 3/4 bits with a resolution of 1/4 bit of the bit period. 3.1.1 input bit delay programming (backplane and local input streams) input bit delay registers lidr0 - 15 and bidr0 - 15 work in conjunction with the smpl_mode bit in the control register to allow users to control input bit fractional delay as well as input bit sample point selection for greater flexibility when designing switch matrices for high speed operation. when smpl_mode = low (input bit fractional delay mode), bits lid[4:0] and bid[4:0] in the lidr0 - 15 and bidr0 - 15 registers respectively define the input bit fractional delay of the corresponding local and backplane stream. the total delay can be up to 7 3/4 bits with a resolution of 1/4 bit at the selected data rate. when smpl_mode = high (sampling point select mode), bits lid[1:0] and bid[1:0] define the input bit sampling point of the stream. the sampling point can be programmed at the 3/4, 4/4, 1/4 or 2/4 bit location to allow better tolerance for input jitter. bits lid[4:2] and bid[4:2] define the integer input bit delay, with a maximum value of 7 bits at a resolution of 1 bit. refer to figure 8 for input bit delay timing at 32mbps data rates. refer to figure 9 for input sampling point selection timing at 32mbps data rates.
ZL50063 data sheet 20 zarlink semiconductor inc. figure 8 - backplane and local input bit delay timing diagram for data rate of 32mbps c8i 72 3 4 5 610 bsti/lsti0-15 bit delay = 0 ch0 74 5 6 ch1 2 310 bsti/lsti0-15 bit delay = 1/4 72 3 4 5 610 bsti/lsti0-15 bit delay = 1 ch0 75 6 ch1 2 310 (default) 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch255 ch255 ch255 bit delay, 1/4 bit delay, 1 bsti/lsti0-15 bit delay = 1/2 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch255 bit delay, 1/2 bsti/lsti0-15 bit delay = 3/4 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch255 bit delay, 3/4 bsti/lsti0-15 bit delay = 7 1/2 72 3 4 5 610 ch255 74 5 6 ch0 210 ch254 bit delay, 7 1/2 bsti/lsti0-15 bit delay = 7 3/4 72 3 4 5 610 ch255 74 5 6 ch0 210 ch254 bit delay, 7 3/4 fp8i smpl_mode = low please refer to control register (section 13.1) for smpl_mode definition .
ZL50063 data sheet 21 zarlink semiconductor inc. figure 9 - backplane and local input bit delay or sampling point selection timing diagram for data rate of 32mbps 3.2 output advancement programming (backplane and local output streams) this feature is used to advance the output channel alignment of individual local or backplane output streams with respect to the frame boundary fp8o . each output stream has its own advancement value that can be programmed by the output advancement registers. the output advancement selection is useful in compensating for various parasitic loading on the serial data output pins. the local and backplane output advancement registers, loar0 - loar15 and boar0 - boar15, are used to control the local and backplane output advancement respectively. the advancement is determined with reference to the internal system clock rate (131.072mhz). the advancement can be 0, -1 cycle, -2 cycles or -3 cycles, which converts to approximately 0ns, -7.6ns, -15ns or -23ns as shown in figure 10. c8i 7 2 3 4 5 6 bsti/lsti0-15 bid[4:0]/lid[4:0] = 00011 b ch0 1 0 ch127 sample at 3/4 point fp8i 7 2 3 4 5 6 bsti/lsti0-15 bid[4:0]/lid[4:0] = 00000 b ch0 1 0 bit delay = 0 bit (default) ch127 sample at 3/4 point smpl_mode = low c8i 7 2 3 4 5 6 bsti/lsti0-15 bid[4:0]/lid[4:0] = 00011 b ch0 1 0 ch127 sample at 2/4 point fp8i 7 2 3 4 5 6 bsti/lsti0-15 bid[4:0]/lid[4:0] = 00000 b ch0 1 0 3/4 sampling (default) ch127 sample at 3/4 point smpl_mode = high please refer to control register (section 13.1) for smpl_mode definition. bit delay = 3/4 bit 2/4 sampling
ZL50063 data sheet 22 zarlink semiconductor inc. figure 10 - local and backplane output advancement timing diagram for data rate of 32mbps 4.0 port high-impedance control the input pins, lors and bors , select whether the local ( lsto0-15 ) and backplane ( bsto0-15 ) output streams, respectively, are set to high impedance at the output of the device itself, or are always driven (active high or active low). setting lors/bors to a low state will configure the output streams, lsto0-15/bsto0-15, to transmit bi-state channel data. setting lors/bors to a high state will configure the output streams, lsto0-15/bsto0-15, of the device to invoke a high impedance output on a per-channel basis. the local/backplane output enable bit ( le/be ) of the local/backplane connection memory has direct per-channel control on the high impedance state of the local/backplane output streams, l/bsto0-15 . programming a low state in the connection memory le/be bit will set the stream output of the device to high impedance for the duration of the channel period. see ?local connection memory bit definition,? on page 30 and ?backplane connection memory bit definition,? on page 31 for programming details. the state of the lors/bors pin is detected and the device configured accordingly during a reset operation, e.g. following power-up. the lors/bors pin is an asynchronous input and is expected to be hard-wired for a particular system application, although it may be driven under logic control if preferred. the local/backplane output enable control in order of highest priority is: reset , ode, osb, le/be. reset (input pin) ode (input pin) osb (control register bit) le/be (local / backplane connection memory bit) lors/bors (input pin) lsto0-15/ bsto0-15 0xxx0high 0xxx1hi-z 10xx0high 10xx1hi-z 110x0high table 1 - local and backplane output enable control priority bit advancement, -1 bit advancement, -2 bit advancement, -3 fp8o system clock bsto/lsto0-15 bit advancement = 0 bsto/lsto0-15 bit advancement = -1 (default) bit advancement = -3 bsto/lsto0-15 bit advancement = -2 bsto/lsto0-15 131.072 mhz ch255 ch255 ch255 ch255 ch0 ch0 ch0 ch0 bit 1 bit 0 bit 7 bit 6 bit 5 bit 1 bit 0 bit 7 bit 6 bit 5 bit 1 bit 0 bit 7 bit 6 bit 5 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 4 bit advancement, 0
ZL50063 data sheet 23 zarlink semiconductor inc. 5.0 data delay through the switching paths serial data which goes into the device is converted into parallel format and written to consecutive locations in the data memory. each data memory location corresponds to the input stream and channel number. channels written to any of the buffers during frame n will be read out during frame n+2. the input bit delay and output bit advancement have no impact on the overall data throughput delay. in the following paragraphs, the data throughput delay ( t ) is represented as a function of st-bus frames, input channel number, ( m ), and output channel number ( n ). for 32.768mbps data rate, there are 512 channels on each stream. the input channel number ( m ) and output channel number ( n ) can therefore have a range of 0 to 511. the data throughput delay under various input channel and output channel conditions can be summarized as: t = 2 frames + (n - m) the data throughput delay ( t ) is: t = 2 frames + (n - m) . assuming that m (input channel) and n (output channel) are equal, we have the figure below, in which the delay between the input data being written and the output data being read is exactly 2 frames. figure 11 - data throughput delay with input ch0 switched to output ch0 110x1hi-z 11100high 11101hi-z 1111xactive (high or low) reset (input pin) ode (input pin) osb (control register bit) le/be (local / backplane connection memory bit) lors/bors (input pin) lsto0-15/ bsto0-15 table 1 - local and backplane output enable control priority (continued) frame frame n frame n+1 frame n+2 frame n+3 frame n+4 frame n+5 frame n data frame n+1data frame n+2 data frame n+3 data frame n+4 data frame n+5 data serial input data serial output data frame n-2 data frame n-1 data frame n data frame n+1 data frame n+2 data frame n+3 data 2 frames + 0
ZL50063 data sheet 24 zarlink semiconductor inc. assuming that n (output channel) is greater than m (input channel), we have the figure below, in which the delay time between the input channel being written and the output channel being read exceeds 2 frames. figure 12 - data throughput delay with input ch0 switched to output ch13 assuming that n (output channel) is less than m (input channel), we have the figure below, in which the delay time between the input channel being written and the output channel being read is less than 2 frames. figure 13 - data throughput delay with input ch13 switched to output ch0 6.0 microprocessor port the 16k switch family supports non-multiplexed motorola type microprocessor buses. the microprocessor port consists of a 16-bit parallel data bus ( d0-15 ), a 15-bit address bus ( a0-14 ) and four control signals ( cs , ds , r/w and dta ). the data bus provides access to the internal registers, the backplane connection and data memories, and the local connection and data memories. each memory has 8,192 locations. see table 5, address map for data and connection memory locations (a14 = 1), for the address mapping. each connection memory can be read or written via the 16-bit microprocessor port. the data memories can only be read (but not written) from the microprocessor port. to prevent the bus ?hanging?, in the event of the switch not receiving a master clock, the microprocessor port shall complete the dta handshake when accessed, but any data read from the bus will be invalid. 7.0 device power-up, initialization and reset 7.1 power-up sequence the recommended power-up sequence is for the v dd_io supply (nominally +3.3v) to be established before the power-up of the v dd_pll and v dd_core supplies (nominally +1.8v). the v dd_pll and v dd_core supplies may be powered up simultaneously, but neither should 'lead' the v dd_io supply by more than 0.3v. all supplies may be powered-down simultaneously. frame frame n frame n+1 frame n+2 frame n+3 frame n+4 frame n+5 frame n data frame n+1data frame n+2 data frame n+3 data frame n+4 data frame n+5 data serial input data serial output data frame n-2 data frame n-1 data frame n data frame n+1 data frame n+2 data frame n+3 data 2 frames + (n - m) frame frame n frame n+1 frame n+2 frame n+3 frame n+4 frame n+5 frame n data frame n+1data frame n+2 data frame n+3 data frame n+4 data frame n+5 data serial input data serial output data frame n-2 data frame n-1 data frame n data frame n+1 data frame n+2 data frame n+3 data 2 frames + (n - m)
ZL50063 data sheet 25 zarlink semiconductor inc. 7.2 initialization upon power up, the device should be initialized by applying the following sequence: 7.3 reset the reset pin is used to reset the device. when set low, an asynchronous reset is applied to the device. it is then synchronized to the internal clock. during the reset period, depending on the state of input pins lors and bors , the output streams lsto0-15 and bsto0-15 are set to high or high impedance, and all internal registers and counters are reset to the default state. the reset pin must remain low for two input clock cycles ( c8i ) to guarantee a synchronized reset release. a delay of an additional 250 s must also be waited before the first microprocessor access is performed following the de-assertion of the reset pin; this delay is required for determination of the frame pulse format. in addition, the reset signal must be de-asserted less than 12 s after the frame boundary or more than 13 s after the frame boundary, as illustrated in figure 14. this can be achieved, for example, by synchronizing the de-assertion of the reset signal with the input frame pulse fp8i . figure 14 - hardware reset de-assertion 1 ensure the trst pin is permanently low to disable the jtag tap controller. 2set ode pin to low. this sets the lsto0-15 outputs to high or high impedance, dependent on the lors input value, and sets the bsto0-15 outputs to high or high impedance, dependent on bors input value. refer to pin description for details of the lors and bors pins. 3 reset the device by asserting the reset pin to zero for at least two cycles of the input clock, c8i . a delay of an additional 250 s must also be applied before the first microprocessor access is performed following the de-assertion of the reset pin; this delay is required for determination of the input frame pulse format. 4 use the block programming mode to initialize the local and the backplane connection memories. refer to section 8.3, connection memory block programming. 5set ode pin to high after the connection memories are programmed to ensure that bus contention will not occur at the serial stream outputs. fp8i reset 12 s 13 s de-assertion of reset must not fall within this window reset assertion reset de-assertion reset (case 1) (case 2)
ZL50063 data sheet 26 zarlink semiconductor inc. 8.0 connection memory the device includes two connection memories, the local connection memory and the backplane connection memory. 8.1 local connection memory the local connection memory (lcm) is a 16-bit wide memory with 8,192 memory locations to support the local output port. the most significant bit of each word, bit[15], selects the source stream from either the backplane (lsrc = low) or the local (lsrc = high) port and determines the backplane-to-local or local-to-local data routing. bits[14:13] select the control modes of the local output streams, the per-channel message mode and the per-channel high impedance output control modes. in connection mode (bit[14] = low), bits[12:0] select the source stream and channel number as detailed in table 2. in message mode (bit[14] = high), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. bit[13] must be high for message mode to ensure that the output channel is not tri-stated. 8.2 backplane connection memory the backplane connection memory (bcm) is a 16-bit wide memory with 8,192 memory locations to support the backplane output port. the most significant bit of each word, bit[15], selects the source stream from either the backplane (bsrc = high) or the local (bsrc = low) port and determines the local-to-backplane or backplane-to-backplane data routing. bit[14:13] select the control modes of the backplane output streams, namely the per-channel message mode and the per-channel high impedance output control mode. in connection mode (bit[14] = low), bits[12:0] select the source stream and channel number as detailed in table 2. in message mode (bit[14] = high), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. bit[13] must be high for message mode to ensure that the output channel is not tri-stated. the control register bits ms[2:0] must be set to 000 to select the local connection memory for the write and read operations via the microprocessor port. the control register bits ms[2:0] must be set to 001 to select the backplane connection memory for the write and read operations via the microprocessor port. see section 6.0, microprocessor port, and section 13.1, control register (cr) for details on microprocessor port access. 8.3 connection memory block programming this feature allows fast, simultaneous, initialization of the local and backplane connection memories after power-up. when the memory block programming mode is enabled, the contents of the block programming register (bpr) will be loaded into the connection memories. see table 11 and table 12 for details of the control register and block programming register values, respectively. 8.3.1 memory block programming procedure: ? set the mbp bit in the control register from low to high. ?set the bpe bit to high in the block programming register (bpr). the local block programming data bits, lbpd[2:0] , of the block programming register, will be loaded into bits[15:13] of the local connection memory. the remaining bit positions are loaded with zeros as shown in table 3. source stream bit rate source stream no. source channel no. 32mbps bits[12:9] legal values 0:15 bits[8:0] legal values 0:511 table 2 - local and backplane connection memory configuration
ZL50063 data sheet 27 zarlink semiconductor inc. table 3 - local connection memory in block programming mode the backplane block programming data bits, bbpd[2:0] , of the block programming register, will be loaded into bits[15:13] respectively, of the backplane connection memory. the remaining bit positions are loaded with zeros as shown in table 4. table 4 - backplane connection memory in block programming mode the block programming register bit, bpe will be automatically reset low within 125 s, to indicate completion of memory programming. the block programming mode can be terminated at any time prior to completion by clearing the bpe bit of the block programming register or the mbp bit of the control register. note that the default values (low) of lbpd[2:0] and bbpd[2:0] of the block programming register, following a device reset, can be used. during reset, all output channels go high or high impedance, depending on the value of the lors and bors pins, irrespective of the values in bits[14:13] of the connection memory. 9.0 memory built-in-self-test (bist) mode as operation of the memory bist will corrupt existing data, this test must only be instigated when the device is placed ?out-of-service? or isolated from live traffic. the memory bist mode is enabled through the microprocessor port ( section 13.7, memory bist register ). internal bist memory controllers generate the memory test pattern (s-march) and control the memory test. the memory test result is monitored through the memory bist register. 10.0 jtag port the ZL50063 jtag interface conforms to the ieee 1149.1 standard. the operation of the boundary-scan circuit shall be controlled by an external test access port (tap) controller. 10.1 test access port (tap) the test access port (tap) consists of four input pins and one output pin described as follows: ? test clock input (tck) tck provides the clock for the tap controller and is independent of any on-chip clock. tck permits the shifting of test data into or out of the boundary-scan register cells under the control of the tap controller in boundary-scan mode. ? test mode select input (tms) the tap controller uses the logic signals applied to the tms input to control test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin in internally pulled to v dd_io when not driven from an external source. 15 14 13 1211109876543210 lbpd2 lbpd1lbpd00000000000000 15 14 13 1211109876543210 bbpd2bbpd1 bbpd0 0000000000000
ZL50063 data sheet 28 zarlink semiconductor inc. ? test data input (tdi) depending on the previously applied data to the tms input, the serial input data applied to the tdi port is connected either to the instruction register or to a test data register. both registers are described in section 10.2, tap registers. the applied input data is sampled at the rising edge of tck pulses. this pin is internally pulled to v dd_io when not driven from an external source. ? test data output (tdo) depending on the previously applied sequence to the tms input, the contents of either the instruction register or data register are serially shifted out towards the tdo . the data out of the tdo is clocked on the falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo output is set to a high impedance state. ? test reset (trst ) trst provides an asynchronous reset to the jtag scan structure. this pin is internally pulled high when not driven from an external source. this pin must be pulled low for normal operation. 10.2 tap registers the ZL50063 implements the public instructions defined in the ieee-1149.1 standard with the provision of an instruction register and three test data registers. 10.2.1 test instruction register the jtag interface contains a four-bit instruction register. instructions are serially loaded into the instruction register from the tdi pin when the tap controller is in the shift-ir state. instructions are subsequently decoded to achieve two basic functions: to select the test data register to operate while the instruction is current, and to define the serial test data register path to shift data between tdi and tdo during data register scanning. please refer to figure 24 for jtag test port timing. 10.2.2 test data registers 10.2.2.1 the boundary-scan register the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the ZL50063 core logic. 10.2.2.2 the bypass register the bypass register is a single stage shift register to provide a one-bit path from tdi to tdo . 10.2.2.3 the device identification register the jtag device id for the ZL50063 is 0c38f14b h . version, bits <31:28>:0000 part no., bits <27:12>:1100 0011 1000 1111 manufacturer id, bits <11:1>:0001 0100 101 header, bit <0> (lsb):1 10.3 boundary scan description language (bsdl) file a boundary scan description language (bsdl) file is available from zarlink semiconductor to aid in the use of the ieee 1149.1 test interface.
ZL50063 data sheet 29 zarlink semiconductor inc. 11.0 memory address mappings when the most significant bit, a14, of the address bus is set to ?1?, the microprocessor performs an access to one of the device?s internal memories. the control register bits ms[2:0] indicate which memory (local connection, local data, backplane connection, or backplane data) is being accessed. address bits a0-a13 indicate which location within the particular memory is being accessed. table 5 - address map for data and connection memory locations (a14 = 1) the device contains two data memory blocks, one for received backplane data and one for received local data. for all data rates, the received data is converted to parallel format by internal serial-to-parallel converters and stored sequentially in the relevant data memory. 11.1 local data memory bit definition the 8-bit local data memory (ldm) has 8,192 positions. the locations are associated with the local input streams and channels. as explained in the section above, address bits a13-a0 of the microprocessor define the addresses of the streams and the channels. the ldm is read-only and configured as follows: note that the local data memory is actually an 8-bit wide memory. the most significant 8 bits expressed in the table above are presented to provide 16-bit microprocessor read accesses. address bit description a14 selects memory or register access (0 = register, 1 = memory). note that which memory (local connection, local data, backplane connection, backplane data) is accessed depends on the ms[2:0] bits in the control register . a13-a9 stream address (0 - 15) streams 0 to 15 are used a8-a0 channel address (0 - 511) channels 0 to 511 are used when serial stream is at 32.768mbps bit name description 15:8 reserved set to a default value of 8?h00. 7:0 ldm local data memory - local input channel data. the ldm[7:0] bits contain the timeslot data from the local side input tdm stream. ldm[7] corresponds to the first bit received, i.e. bit 7 in st-bus mode, bit 0 in gci-bus mode. see figure 6, st-bus and gci-bus input timing diagram for the arrival order of the bits. table 6 - local data memory (ldm) bits
ZL50063 data sheet 30 zarlink semiconductor inc. 11.2 backplane data memory bit definition the 8-bit backplane data memory (bdm) has 8,192 positions. the locations are associated with the backplane input streams and channels. as explained previously, address bits a13-a0 of the microprocessor define the addresses of the streams and the channels. the bdm is read-only and configured as follows: note that the backplane data memory is actually an 8-bit wide memory. the most significant 8 bits expressed in the table above are presented to provide 16-bit microprocessor read accesses. 11.3 local connection memory bit definition the local connection memory (lcm) has 8,192 addresses of 16-bit words. each address, accessed through bits a13-a0 of the microprocessor port, is allocated to an individual local output stream and channel. the bit definition for each 16-bit word is presented in table 8 for source-to-local connections. the most-significant bit in the memory location, lsrc, selects the switch configuration for backplane-to-local or local-to-local. when the per-channel message mode is selected (lmm memory bit = high), the lower byte of the lcm word (lcab[7:0]) will be transmitted as data on the output stream (lsto0-15) in place of data defined by the source control, stream and channel address bits. bit name description 15:8 reserved set to a default value of 8?h00. 7:0 bdm backplane data memory - backplane input channel data. the bdm[7:0] bits contain the timeslot data from the backplane side input tdm stream. bdm[7] corresponds to the first bit received, i.e. bit 7 in st-bus mode, bit 0 in gci-bus mode. see figure 6, st-bus and gci-bus input timing diagram for the arrival order of the bits. table 7 - backplane data memory (bdm) bits bit name description 15 lsrc local source control bit when low, the source is from the backplane input port (backplane data memory). when high, the source is from the local input port (local data memory). ignored when lmm is set high. 14 lmm local message mode bit when low, the channel is in connection mode (data to be output on channel originated in local or backplane data memory). when high, the channel is in message mode (data to be output on channel originated in local connection memory). 13 le local output enable bit when low, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the lors pin. when high, the channel is active. 12:9 lsab[3:0] source stream address bits the binary value of these 4 bits represents the input stream number. ignored when lmm is set high. table 8 - lcm bits for source-to-local switching
ZL50063 data sheet 31 zarlink semiconductor inc. 11.4 backplane connection memory bit definition the backplane connection memory (bcm) has 8,192 addresses of 16-bit words. each address, accessed through bits a13-a0 of the microprocessor port, is allocated to an individual backplane output stream and channel. the bit definition for each 16-bit word is presented in table 9 for source-to-backplane connections. the most-significant bit in the memory location, bsrc, selects the switch configuration for local-to-backplane or backplane-to-backplane. when the per-channel message mode is selected (bmm memory bit = high), the lower byte of the bcm word (bcab[7:0]) will be transmitted as data on the output stream (bsto0-15) in place of data defined by the source control, stream and channel address bits. table 9 - bcm bits for source-to-backplane switching 8:0 lcab[8:0] source channel address bits / message mode data the binary value of these 9 bits represents the input channel number, when lmm is low. bits lcab[7:0] transmitted as data when lmm is set high. note: when lmm is set high, in both st-bus and gci-bus modes, the lcab[7:0] bits are output sequentially to the timeslot with lcab[7] being output first. bit name description 15 bsrc backplane source control bit when low, the source is from the local input port (local data memory). when high, the source is from the backplane input port (backplane data memory). ignored when bmm is set high. 14 bmm backplane message mode bit when low, the channel is in connection mode (data to be output on channel originated in backplane or local data memory). when high, the channel is in message mode (data to be output on channel originated in backplane connection memory). 13 be backplane output enable bit when low, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the bors pin. when high, the channel is active. 12:9 bsab[3:0] source stream address bits the binary value of these 4 bits represents the input stream number. ignored when bmm is set high. 8:0 bcab[8:0] source channel address bits / message mode data the binary value of these 9 bits represents the input channel number, when bmm is low. bits bcab[7:0] transmitted as data when bmm is set high. note: when bmm is set high, in both st-bus and gci-bus modes, the bcab[7:0] bits are output sequentially to the timeslot with bcab[7] being output first. bit name description table 8 - lcm bits for source-to-local switching (continued)
ZL50063 data sheet 32 zarlink semiconductor inc. 12.0 internal register mappings when the most significant bit, a14, of the address bus is set to ?0?, the microprocessor is performing an access to one of the device?s internal registers. address bits a13-a0 indicate which particular register is being accessed. 13.0 detailed register descriptions this section describes the registers that are used in the device. 13.1 control register (cr) address 0000 h . the control register defines which memory is to be accessed. it initiates the memory block programming mode and selects the backplane and local data rate modes. the control register ( cr ) is configured as follows: a14-a0 register 0000 h control register, cr 0001 h block programming register, bpr 0023 h - 0032 h local input bit delay register 0 - 15, lidr0 - 15 0063 h - 0072 h backplane input bit delay register 0 - 15, bidr0 - 15 0083 h - 0092 h local output advancement register 0 - 15, loar0 - 15 00a3 h - 00b2 h backplane output advancement register 0 - 15, boar0 - 15 014d h memory bist register, mbistr 3fff h device identification register, dir table 10 - address map for registers (a14 = 0) bit name reset value description 15:13 fbd_ mode[2:0] 0 frame boundary discriminator mode when set to 111 b , the frame boundary discriminator can handle both low frequency and high frequency jitter. when set to 000 b , the frame boundary discriminator is set to handle lower frequency jitter only. all other values are reserved. these bits are ignored when fbden bit is low. 12 smpl_ mode 0 sample point mode when low the input bit sampling point is always at the 3/4 bit location. the input bit fractional delay is programmed in 1/4 bit increments from 0 to 7 3/4 as per the value of the lidr0 to lidr15 and bidr0 to bidr15 registers. when high, the input bit sampling point is programmed to the 3/4, 4/4, 1/4, 2/4 bit location as per the value of the lidr0 to lidr15 and bidr0 to bidr15 registers. in addition the incoming data can be delayed by 0 to 7 bits in 1 bit increments. see table 13, table 14, table 15 and table 16 for details. 11 reserved 0 reserved must be set to 0 for normal operation table 11 - control register bits
ZL50063 data sheet 33 zarlink semiconductor inc. 10 fbden 0 frame boundary discriminator enable when low, the frame boundary discriminator function is disabled. when high, enables frame boundary discriminator function which allows the device to tolerate inconsistent frame boundaries, hence improving the tolerance to cycle-to-cycle variation on the input clock. 9 reserved 0 reserved must be set to 0 for normal operation 8fpw 0 frame pulse width when low, the user must apply a 122ns frame pulse on fp8i ; the fp8o pin will output a 122ns wide frame pulse; fp16o will output a 61ns wide frame pulse. when high, the user must apply a 244ns frame pulse on fp8i ; the fp8o pin will output a 244ns wide frame pulse; fp16o will output a 122ns wide frame pulse. 7 reserved 0 reserved must be set to 0 for normal operation 6c8ipol 0 8mhz input clock polarity the frame boundary is aligned to the falling or rising edge of the input clock. when low, the frame boundary is aligned to the clock falling edge. when high, the frame boundary is aligned to the clock rising edge. 5 copol 0 output clock polarity when low, the output clock has the same polarity as the input clock. when high, the output clock is inverted. this applies to both the 8mhz (c8o ) and 16mhz (c16o ) output clocks. 4mbp 0 memory block programming when low, the memory block programming mode is disabled. when high, the connection memory block programming mode is ready to program the local connection memory (lcm) and the backplane connection memory (bcm). 3osb 0 output stand by this bit enables the bsto0-15 and lsto0-15 serial outputs . when low, bsto0-15 and lsto0-15 are driven high or high impedance, dependent on the bors and lors pin settings respectively. when high, bsto0-15 and lsto0-15 are enabled. 2 reserved 0 reserved must be set to 0 for normal operation 1:0 ms[1:0] 0 memory select bits these three bits select the connection or data memory for subsequent microport memory access operations: 00 selects local connection memory (lcm) for read or write operations. 01 selects backplane connection memory (bcm) for read or write operations. 10 selects local data memory (ldm) for read-only operation. 11 selects backplane data memory (bdm) for read-only operation. bit name reset value description table 11 - control register bits (continued) output control with ode pin and osb bit ode pin osb bit bsto0-15, lsto0-15 0x disabled 10 disabled 1 1 enabled
ZL50063 data sheet 34 zarlink semiconductor inc. figure 15 - frame boundary conditions, st-bus operation frame boundary c8i fp8i frame pulse width = 122ns, control register bit8 (fpw) = 0 control register bit6 (c8ipol) = 0 (a) frame pulse width = 122ns, control register bit8 (fpw) = 0 control register bit6 (c8ipol) = 1 (b) frame pulse width = 244ns, control register bit8 (fpw) = 1 control register bit6 (c8ipol) = 0 (c) frame pulse width = 244ns, control register bit8 (fpw) = 1 control register bit6 (c8ipol) = 1 (d) c8i fp8i c8i fp8i c8i fp8i
ZL50063 data sheet 35 zarlink semiconductor inc. figure 16 - frame boundary conditions, gci-bus operation frame boundary pulse width = 122ns, control register bit8 (fpw) = 0 control register bit6 (c8ipol) = 0 (e) pulse width = 122ns, control register bit8 (fpw) = 0 control register bit6 (c8ipol) = 1 (f) pulse width = 244ns, control register bit8 (fpw) = 1 control register bit6 (c8ipol) = 0 (g) pulse width = 244ns, control register bit8 (fpw) = 1 control register bit6 (c8ipol) = 1 (h) c8i fp8i c8i fp8i c8i fp8i c8i fp8i
ZL50063 data sheet 36 zarlink semiconductor inc. 13.2 block programming register (bpr) address 0001 h . the block programming register stores the bit patterns to be loaded into the connection memories when the memory block programming feature is enabled. the bpe, lbpd[2:0] and bbpd[2:0] bits in the bpr register must be defined in the same write operation. the bpe bit is set high to commence the block programming operation. programming is completed in one frame period and may be initiated at any time within a frame. the bpe bit returns to low to indicate that the block programming function has completed. when bpe is high, no other bits of the bpr register may be changed for at least a single frame period, except to abort the programming operation. the programming operation may be aborted by setting either bpe to low, or the control register bit, mbp, to low. the bpr register is configured as follows. . table 12 - block programming register bits bit name reset value description 15:7 reserved 0 reserved must be set to 0 for normal operation 6:4 bbpd[2:0] 0 backplane block programming data these bits refer to the value loaded into the backplane connection memory (bcm) when the memory block programming feature is activated. when the mbp bit in the control register (cr) is set high and bpe (in this register) is set high, the contents of bits bbpd[2:0] are loaded into bits 15-13, respectively, of the bcm. bits 12-0 of the bcm are set low. 3:1 lbpd[2:0] 0 local block programming data these bits refer to the value loaded into the local connection memory (lcm), when the memory block programming feature is activated. when the mbp bit in the control register is set high and bpe (in this register) is set high, the contents of bits lbpd[2:0] are loaded into bits 15-13, respectively, of the lcm. bits 12-0 of the lcm are set low. 0bpe 0 block programming enable a low to high transition of this bit enables the memory block programming function. a low will be returned after 125 s, upon completion of programming. set low to abort the programming operation.
ZL50063 data sheet 37 zarlink semiconductor inc. 13.3 local input bit delay registers (lidr0 to lidr15) addresses 0023 h to 0032 h . there are sixteen local input delay registers (lidr0 to lidr15). when the smpl_mode bit in the control register is low, the input data sampling point defaults to the 3/4 bit location and lidr0 to lidr15 define the input bit and fractional bit delay of each local stream. the possible bit delay adjustment is up to 7 3 / 4 bits, in steps of 1 / 4 bit. when the smpl_mode bit is high, lidr0 to lidr15 define the input bit sampling point as well as the integer bit delay of each local stream. the input bit sampling point can be adjusted in 1/4 bit increments. the bit delay can be adjusted in 1-bit increments from 0 to 7 bits. the lidr0 to lidr15 registers are configured as follows: table 13 - local input bit delay register (lidrn) bits 13.3.1 local input delay bits 4-0 (lid[4:0]) when smpl_mode = low, these five bits define the amount of input bit delay adjustment that the receiver uses to sample each input. input bit delay adjustment can range up to 7 3 / 4 bit periods forward, with resolution of 1 / 4 bit period. the default sampling point is at the 3 / 4 bit location. this can be described as: no. of bits delay = lid[4:0] / 4 for example, if lid[4:0] is set to 10011 (19), the input bit delay = 19 * 1 / 4 = 4 3 / 4 . when smpl_mode = high, the binary value of lid[1:0] refers to the input bit sampling point ( 1 / 4 to 4 / 4 ). lid[4:2] refers to the integer bit delay value (0 to 7 bits). this means that bits can be delayed by an integer value of up to 7 and that the sampling point can vary from 1 / 4 to 4 / 4 in 1 / 4 bit increments. table 14 illustrates the bit delay and sampling point selection. lidrn bit (where n = 0 to 15) name reset value description 15:5 reserved 0 reserved must be set to 0 for normal operation 4:0 lid[4:0] 0 local input bit delay register when smpl_mode = low, the binary value of these bits refers to the input bit and fractional bit delay value (0 to 7 3 / 4 ). when smpl_mode = high, the binary value of lid[1:0] refers to the input bit sampling point ( 1 / 4 to 4 / 4 ). lid[4:2] refers to the integer bit delay value (0 to 7 bits). lidn smpl_mode = low smpl_mode = high lid4 lid3 lid2 lid1 lid0 input data bit delay input data bit delay input data sampling point 000000 (default)0 (default) 3/4 00001 1/4 0 4/4 table 14 - local input bit delay and sampling point programming table
ZL50063 data sheet 38 zarlink semiconductor inc. 00010 1/2 0 1/4 00011 3/4 0 2/4 00100 1 1 3/4 00101 1 1/4 1 4/4 00110 1 1/2 1 1/4 00111 1 3/4 1 2/4 01000 2 2 3/4 01001 2 1/4 2 4/4 01010 2 1/2 2 1/4 01011 2 3/4 2 2/4 01100 3 3 3/4 01101 3 1/4 3 4/4 01110 3 1/2 3 1/4 01111 3 3/4 3 2/4 10000 4 4 3/4 10001 4 1/4 4 4/4 10010 4 1/2 4 1/4 10011 4 3/4 4 2/4 10100 5 5 3/4 10101 5 1/4 5 4/4 10110 5 1/2 5 1/4 10111 5 3/4 5 2/4 11000 6 6 3/4 11001 6 1/4 6 4/4 11010 6 1/2 6 1/4 11011 6 3/4 6 2/4 11100 7 7 3/4 11101 7 1/4 7 4/4 11110 7 1/2 7 1/4 11111 7 3/4 7 2/4 lidn smpl_mode = low smpl_mode = high lid4 lid3 lid2 lid1 lid0 input data bit delay input data bit delay input data sampling point table 14 - local input bit delay and sampling point programming table (continued)
ZL50063 data sheet 39 zarlink semiconductor inc. 13.4 backplane input bit delay registers (bidr0 to bidr15) addresses 0063 h to 0072 h there are sixteen backplane input delay registers (bidr0 to bidr15). when the smpl_mode bit in the control register is low, the input data sampling point defaults to the 3/4 bit location and bidr0 to bidr15 define the input bit and fractional bit delay of each backplane stream. the possible bit delay adjustment is up to 7 3 / 4 bits, in steps of 1 / 4 bit. when the smpl_mode bit is high, bidr0 to bidr15 define the input bit sampling point as well as the integer bit delay of each backplane stream. the input bit sampling point can be adjusted in 1/4 bit increments. the bit delay can be adjusted in 1-bit increments from 0 to 7 bits. the bidr0 to bidr15 registers are configured as follows: table 15 - backplane input bit delay register (bidrn) bits 13.4.1 backplane input delay bits 4-0 (bid[4:0]) when smpl_mode = low, these five bits define the amount of input bit delay adjustment that the receiver uses to sample each input. input bit delay adjustment can range up to 7 3 / 4 bit periods forward, with resolution of 1 / 4 bit period. the default sampling point is at the 3 / 4 bit location. this can be described as: no. of bits delay = bid[4:0] / 4 for example, if bid[4:0] is set to 10011 (19), the input bit delay = 19 * 1 / 4 = 4 3 / 4. when smpl_mode = high, the binary value of bid[1:0] refers to the input bit sampling point ( 1 / 4 to 4 / 4 ). bid[4:2] refers to the integer bit delay value (0 to 7 bits). this means that bits can be delayed by an integer value of up to 7 and that the sampling point can vary from 1 / 4 to 4 / 4 in 1 / 4 bit increments. table 16 illustrates the bit delay and sampling point selection. bidrn bit (where n = 0 to 15) name reset value description 15:5 reserved 0 reserved must be set to 0 for normal operation 4:0 bid[4:0] 0 backplane input bit delay register when smpl_mode = low, the binary value of these bits refers to the input bit fractional delay value (0 to 7 3 / 4 ). when smpl_mode = high, the binary value of bid[1:0] refers to the input bit sampling point ( 1 / 4 to 4 / 4 ). bid[4:2] refers to the integer bit delay value (0 to 7 bits). bidn smpl_mode = low smpl_mode = high bid4 bid3 bid2 bid1 bid0 input data bit delay input data bit delay input data sampling point 000000 (default)0 (default) 3/4 00001 1/4 0 4/4 table 16 - backplane input bit delay and sampling point programming table
ZL50063 data sheet 40 zarlink semiconductor inc. 00010 1/2 0 1/4 00011 3/4 0 2/4 00100 1 1 3/4 00101 1 1/4 1 4/4 00110 1 1/2 1 1/4 00111 1 3/4 1 2/4 01000 2 2 3/4 01001 2 1/4 2 4/4 01010 2 1/2 2 1/4 01011 2 3/4 2 2/4 01100 3 3 3/4 01101 3 1/4 3 4/4 01110 3 1/2 3 1/4 01111 3 3/4 3 2/4 10000 4 4 3/4 10001 4 1/4 4 4/4 10010 4 1/2 4 1/4 10011 4 3/4 4 2/4 10100 5 5 3/4 10101 5 1/4 5 4/4 10110 5 1/2 5 1/4 10111 5 3/4 5 2/4 11000 6 6 3/4 11001 6 1/4 6 4/4 11010 6 1/2 6 1/4 11011 6 3/4 6 2/4 11100 7 7 3/4 11101 7 1/4 7 4/4 11110 7 1/2 7 1/4 11111 7 3/4 7 2/4 bidn smpl_mode = low smpl_mode = high bid4 bid3 bid2 bid1 bid0 input data bit delay input data bit delay input data sampling point table 16 - backplane input bit delay and sampling point programming table (continued)
ZL50063 data sheet 41 zarlink semiconductor inc. 13.5 local output advancement registers (loar0 to loar15) addresses 0083 h to 0092 h . sixteen local output advancement registers (loar0 to loar15) allow users to program the output advancement for output data streams lsto0 to lsto15. the possible adjustment is -1 (7.6ns), -2 (15ns) or -3 (23ns) cycles of the internal system clock (131.072mhz). the loar0 to loar15 registers are configured as follows: table 17 - local output advancement register (loar) bits 13.5.1 local output advancement bits 1-0 (loa1-loa0) the binary value of these two bits indicates the amount of offset that a particular stream output can be advanced with respect to the output frame boundary. when the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse fp8o . loarn bit (where n = 0 to 15) name reset value description 15:2 reserved 0 reserved must be set to 0 for normal operation 1:0 loa[1:0] 0 local output advancement value local output advancement corresponding advancement bits clock rate 131.072 mhz loa1 loa0 0 (default) 0 0 -1 cycle (~7.6ns) 0 1 -2 cycles (~15ns) 1 0 -3 cycles (~23ns) 1 1 table 18 - local output advancement (loar) programming table
ZL50063 data sheet 42 zarlink semiconductor inc. 13.6 backplane output advancement registers (boar0 - boar15) addresses 00a3 h to 00b2 h sixteen backplane output advancement registers (boar0 to boar15) allow users to program the output advancement for output data streams bsto0 to bsto15. the possible adjustment is -1 (7.6ns), -2 (15ns) or -3 (23ns) cycles of the internal system clock (131.072mhz). the boar0 to boar15 registers are configured as follows: table 19 - backplane output advancement register (boar) bits 13.6.1 backplane output advancement bits 1-0 (boa1-boa0) the binary value of these two bits indicates the amount of offset that a particular stream output can be advanced with respect to the output frame boundary. when the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse fp8o . boarn bit (where n = 0 to 15) name reset value description 15:2 reserved 0 reserved must be set to 0 for normal operation 1:0 boa[1:0] 0 backplane output advancement value backplane output advancement corresponding advancement bits clock rate 131.072 mhz boa1 boa0 0 (default) 0 0 -1 cycle (~7.6ns) 0 1 -2 cycles (~15ns) 1 0 -3 cycles (~23ns) 1 1 table 20 - backplane output advancement (boar) programming table
ZL50063 data sheet 43 zarlink semiconductor inc. 13.7 memory bist register address 014d h . the memory bist register enables the self-test of chip memory. two consecutive write operations are required to start mbist: the first with only bit 12 (lv_tm) set high (i.e. 1000h); the second with bit 12 maintained high but with the required start bit(s) also set high. the mbistr register is configured as follows: bit name reset value description 15:13 reserved 0 reserved must be set to 0 for normal operation 12 lv_tm 0 mbist test enable set high to enable mbist mode. set low for normal operation. 11 bistsdb 0 backplane data memory start bist sequence sequence enabled on low to high transition. 10 bistcdb 0 backplane data memory bist sequence completed (read-only) this bit must be polled - when high, indicates completion of backplane data memory bist sequence. 9bistpdb 0 backplane data memory pass/fail bit (read-only) this bit indicates the pass/fail status following completion of the backplane data memory bist sequence (indicated by assertion of bistcdb). a high indicates pass, a low indicates fail. 8bistsdl 0 local data memory start bist sequence sequence enabled on low to high transition. 7 bistcdl 0 local data memory bist sequence completed (read-only) this bit must be polled - when high, indicates completion of local data memory bist sequence. 6bistpdl 0 local data memory pass/fail bit (read-only) this bit indicates the pass/fail status following completion of the local data memory bist sequence (indicated by assertion of bistcdl). a high indicates pass, a low indicates fail. 5bistscb 0 backplane connection memory start bist sequence sequence enabled on low to high transition. 4bistccb 0 backplane connection memory bist sequence completed (read-only) this bit must be polled - when high, indicates completion of backplane connection memory bist sequence. 3bistpcb 0 backplane connection memory pass/fail bit (read-only) this bit indicates the pass/fail status following completion of the backplane connection memory bist sequence (indicated by assertion of bistccb). a high indicates pass, a low indicates fail. table 21 - memory bist register (mbistr) bits
ZL50063 data sheet 44 zarlink semiconductor inc. 13.8 device identification register address 3fff h . the device identification register stores the binary value of the silicon revision number and the device id. this register is read-only. the dir register is configured as follows: table 22 - device identification register (dir) bits 2bistscl 0 local connection memory start bist sequence sequence enabled on low to high transition. 1 bistccl 0 local connection memory bist sequence completed (read-only) this bit must be polled - when high, indicates completion of local connection memory bist sequence. 0bistpcl 0 local connection memory pass/fail bit (read-only) this bit indicates the pass/fail status following completion of the local connection memory bist sequence (indicated by assertion of bistccl). a high indicates pass, a low indicates fail. bit name reset value description 15:8 reserved 0 reserved will be set to 0 in normal operation 7:4 rc[3:0] 0000 revision control bits 3 reserved 0 reserved will be set to 0 in normal operation 2:0 did[2:0] 011 device id bit name reset value description table 21 - memory bist register (mbistr) bits (continued)
ZL50063 data sheet 45 zarlink semiconductor inc. 14.0 dc electrical characteristics * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. voltages are with respect to ground (v ss ) unless otherwise stated. absolute maximum ratings* parameter symbol min max units 1 core supply voltage v dd_core -0.5 2.5 v 2 i/o supply voltage v dd_io -0.5 5.0 v 3 pll supply voltage v dd_pll -0.5 2.5 v 4 input voltage (non-5v tolerant inputs) v i -0.5 v dd_io +0.5 v 5 input voltage (5v tolerant inputs) v i_5v -0.5 7.0 v 6 continuous current at digital outputs i o 15 ma 7 package power dissipation p d 1.5 w 8 storage temperature t s - 55 +125 c recommended operating conditions characteristics sym min typ max units 1 operating temperature t op -40 25 +85 c 2 positive supply v dd_io 3.0 3.3 3.6 v 3 positive supply v dd_core 1.71 1.8 1.89 v 4 positive supply v dd_pll 1.71 1.8 1.89 v 5 input voltage v i 0v dd_io v 6 input voltage on 5v tolerant inputs v i_5v 05.5v
ZL50063 data sheet 46 zarlink semiconductor inc. voltages are with respect to ground (v ss ) unless otherwise stated. note 1: maximum leakage on pins (output or i/o pins in high impedance state) is over an applied voltage (v) dc electrical parameters characteristics sym min typ max units test conditions 1a 1b i n p u t s supply current i dd_core 4mastatic i dd_core and pll current supply current i dd_core 240 290 ma applied clock c8i = 8.192 mhz 1c supply current i dd_io 100 astatic i dd_io 1d supply current i dd_io 14 18 ma i av with all output streams at max. data rate unloaded 2 input high voltage v ih 2.0 v 3 input low voltage v il 0.8 v 4 input leakage (input pins) input leakage (bi-directional pins) i il i bl 5 5 a a 0 < v < v dd_io note 1 weak pullup current i pu 200 a input at 0v 5 weak pulldown current i pd 200 a input at v dd_io 6 input pin capacitance c i 5pf 7o u t p u t s output high voltage v oh 2.4 v i oh = 8ma 8 output low voltage v ol 0.4 v i ol = 8ma 9 high-impedance leakage i oz 5 a0 < v 0 < v dd_io note 1 10 output pin capacitance c o 5pf
ZL50063 data sheet 47 zarlink semiconductor inc. 15.0 ac electrical characteristics ac electrical characteristics timing parameter measurement: voltage levels characteristics sym level units conditions 1 cmos threshold v ct 0.5v dd_io v3.0v < v dd_io < 3.6v 2 rise/fall threshold voltage high v hm 0.7v dd_io v3.0v < v dd_io < 3.6v 3 rise/fall threshold voltage low v lm 0.3v dd_io v3.0v < v dd_io < 3.6v input and output clock timing characteristic sym min typ max units notes 1fp8i , input frame pulse width t ifpw244 t ifpw122 210 10 244 122 350 220 ns 2 input frame pulse setup time (before c8i clock falling/rising edge) t ifps244 t ifps122 5 5 110 60 ns 3 input frame pulse hold time (from c8i clock falling/rising edge) t ifph244 t ifph122 0 0 110 60 ns 4c8i clock period (average value, does not consider the effects of jitter) t icp 120 122 124 ns 5c8i clock pulse width high t ich 50 61 70 ns 6c8i clock pulse width low t icl 50 61 70 ns 7c8i clock rise/fall time t ric , t fic 02 3 ns 8c8i cycle to cycle variation (this values is with respect to the typical c8i clock period, and using mid-bit sampling) t ccvic -7.0 -8.5 7.0 8.5 ns 32mbps 9 output frame boundary offset t ofbos 79.5ns 10 fp8o frame pulse width t ofpw8_244 t ofpw8_122 224 117 244 122 264 127 ns fpw =1 fpw=0 c l =60pf 11 fp8o output delay (from frame pulse edge to output frame boundary) t fpfbf8_244 t fpfbf8_122 117 58 122 61 127 64 ns fpw =1 fpw=0 c l =60pf 12 fp8o output delay (from output frame boundary to frame pulse edge) t fbfpf8_244 t fbfpf8_122 117 58 122 61 127 64 ns fpw =1 fpw=0 c l =60pf 13 c8o clock period t ocp8 117 122 127 ns c l =60pf 14 c8o clock pulse width high t och8 58 61 64 ns 15 c8o clock pulse width low t ocl8 58 61 64 ns 16 c8o clock rise/fall time t roc8 , t foc8 37ns
ZL50063 data sheet 48 zarlink semiconductor inc. 17 fp16o frame pulse width t ofpw16_122 t ofpw16_61 117 58 122 61 127 64 ns fpw =1 fpw=0 c l =60pf 18 fp16o output delay (from frame pulse edge to output frame boundary) t fpfbf16_122 t fpfbf16_61 58 29 61 31 64 33 ns fpw =1 fpw=0 19 fp16o output delay (from output frame boundary to frame pulse edge) t fbfpf16_122 t fbfpf16_61 58 29 61 31 64 33 ns fpw =1 fpw=0 20 c16o clock period t ocp16 58 61 64 ns c l =60pf 21 c16o clock pulse width high t och16 29 31 33 ns 22 c16o clock pulse width low t ocl16 29 31 33 ns 23 c16o clock rise/fall time t roc16 , t foc16 37ns input and output clock timing (continued) characteristic sym min typ max units notes
ZL50063 data sheet 49 zarlink semiconductor inc. figure 17 - input and output clock timing diagram for st-bus t ifpw122 t ifph122 t ifps122 ck_int * t fbfpf8_122 t fpfbf8_122 t fpfb16_61 t och8 t ocl8 t ocl16 t och16 t ocp8 t ocp16 t foc8 t roc8 t roc16 t foc16 t ofbos note *: ck_int is the internal clock signal of 131.072mhz f p8o c8o fp16o c16o f p8i c8i t ich t icl t icp t fic t ric t fbfpf8_244 t fpfbf8_244 t ifpw244 t ifph244 t ifps244 f p8i f p8o (244ns) (122ns) (244ns) (122ns) t ofpw8_122 t ofpw16_61 t fbfpf16_122 t fpfbf16_122 fp 16o (122ns) t ofpw8_244 t ofpw16_122 (61ns) t fbfp16_61 note **: although the figures above show the frame boundary as measured from the falling edge of c8i /c8o /c16o , the frame-controlling edge of c8i /c8o /c16o may be the rising edge, as configured via the c8ipol and copol bits of the control register.
ZL50063 data sheet 50 zarlink semiconductor inc. figure 18 - input and output clock timing diagram for gci-bus t ifpw122 t ifph122 t ifps122 ck_int * t fbfpf8_122 t fpfbf8_122 t fpfb16_61 t och8 t ocl8 t ocl16 t och16 t ocp8 t ocp16 t foc8 t roc8 t roc16 t foc16 t ofbos note *: ck_int is the internal clock signal of 131.072mhz f p8o c8o fp16o c16o f p8i c8i t ich t icl t fic t ric t fbfpf8_244 t fpfbf8_244 t ifph244 t ifps244 f p8i f p8o (244ns) (122ns) (244ns) (122ns) t ofpw8_122 t ofpw16_61 t fbfpf16_122 t fpfbf16_122 fp 16o (122ns) t ofpw8_244 t ofpw16_122 (61ns) t fbfp16_61 note **: although the figures above show the frame boundary as measured from the rising edge of c8i /c8o /c16o , the frame-controlling edge of c8i /c8o /c16o may be the rising edge, as configured via the c8ipol and copol bits of the control register. t ifpw244 t icp
ZL50063 data sheet 51 zarlink semiconductor inc. local and backplane data timing characteristic sym min typ max units notes 1 local/backplane input data sampling point t ids32 20 23 26 ns with smpl_mode = 0 (3/4-bit sampling) and zero offset. 2 local/backplane serial input set-up time t sis32 2 ns with respect to min . input data sampling point 3 local/backplane serial input hold time t sih32 2 ns with respect to max . input data sampling point 4 output frame boundary offset t ofbos 79.5ns 5 local/backplane serial output delay t sod32 4.5 ns c l =50pf these numbers are referencing output frame boundary.
ZL50063 data sheet 52 zarlink semiconductor inc. figure 19 - st-bus local/backplane data timing diagram (32mbps) ck_int * fp8 o c8 o l/bsti0-15 l/bsto0-15 t ids32 32.768mbps 32.768mbps t sih32 t sis32 t sod32 bit7 ch0 bit6 ch0 bit1 ch511 bit0 ch511 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 6 5 0 4 3 2 1 7 note *: ck_int is the internal clock signal of 131.072mhz 2 bit1 ch511 ck_int * fp8i c8i t ofbos
ZL50063 data sheet 53 zarlink semiconductor inc. figure 20 - gci-bus local/backplane data timing diagram (32mbps) ck_int * fp8i c8i l/bsti0-15 l/bsto0-15 t ids32 32.768mbps 32.768mbps t sih32 t sis32 t sod32 bit0 ch0 bit1 ch0 bit6 ch511 bit7 ch511 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch0 6 5 0 4 3 2 1 7 note *: ck_int is the internal clock signal of 131.072mhz 2 bit5 ch511 ck_int * fp8 o c8 o t ofbos
ZL50063 data sheet 54 zarlink semiconductor inc. note 1: high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . figure 21 - serial output and external control figure 22 - output driver enable (ode) local and backplane output high-impedance timing characteristic sym min typ max unit s test conditions 1 sto delay - active to high-z - high-z to active t dz t zd 4 4 6 6 ns ns r l =1k, c l =50pf, see note 1 2 output driver enable (ode) delay to active data output driver enable (ode) delay to high-impedance t ode t odz 14 14 ns ns r l =1k, c l =50pf, see note 1 r l =1k, c l =50pf, see note 1 t dz sto t zd sto clk vtt vtt hiz valid data vtt hiz valid data vtt hi-z hi-z sto ode t odz t ode valid data vtt
ZL50063 data sheet 55 zarlink semiconductor inc. input clock jitter tolerance jitter frequency 32.768mbps data rate jitter tolerance units 1 1khz 600 ns 2 10khz 600 ns 3 50khz 80 ns 4 66khz 50 ns 5 83khz 35 ns 6 95khz 30 ns 7 100khz 20 ns 8 200khz 14 ns 9 300khz 14 ns 10 400khz 14 ns 11 500khz 14 ns 12 1mhz 14 ns 13 2mhz 14 ns 14 4mhz 14 ns
ZL50063 data sheet 56 zarlink semiconductor inc. note 1: high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: there must be a minimum of 30ns between cpu accesses, to allow the device to recognize the accesses as separate (i.e., a minimum of 30ns must separate the de-assertion of dta (to high) and the assertion of cs and/or ds to initiate the next access). non-multiplexed microprocessor port timing characteristics sym min typ max units test conditions 1cs setup from ds falling t css 0ns 2r/w setup from ds falling t rws 9ns 3 address setup from ds falling t ads 9ns 4cs hold after ds rising t csh 0ns 5r/w hold after ds rising t rwh 9ns 6 address hold after ds rising t adh 9ns 7 data setup from dta low on read t rds 5 12 ns ns memory read register read c l =60pf 8 data hold on read t rdh 4.5 ns c l =60pf, r l =1k note 1 9 data setup on write t wds 9ns 10 data hold on write t wdh 9ns 11 acknowledgment delay: reading/writing registers reading/writing memory t akd 88 80 ns ns c l =60pf c l =60pf 12 acknowledgment hold time t akh 11 ns c l =60pf, r l =1k, note 1
ZL50063 data sheet 57 zarlink semiconductor inc. figure 23 - motorola non-multiplexed bus timing a0-a14 d0-d15 d0-d15 read write t css t csh t adh t rdh t rws t ads t rwh t wdh t akd t rds t akh v tt v tt v tt v tt v tt v tt v tt valid address valid read data valid write data dta r/w cs ds t wds
ZL50063 data sheet 58 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. figure 24 - jtag test port timing diagram ac electrical characteristics ? - jtag test port timing characteristic sym min typ max units notes 1 tck clock period t tckp 100 ns 2 tck clock pulse width high t tckh 80 ns 3 tck clock pulse width low t tckl 80 ns 4 tms set-up time t tmss 10 ns 5 tms hold time t tmsh 10 ns 6 tdi input set-up time t tdis 20 ns 7 tdi input hold time t tdih 60 ns 8 tdo output delay t tdod 30 ns c l =30pf 9trst pulse width t trstw 200 ns t tmsh t tmss t tckl t tckh t tckp t tdis t tdih t tdod t trstw tms tck tdi tdo trst
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes: conforms to jedec ms - 034 except dimensions 'a1' and 'b'. 2 layers (4 layers) 1. controlling dimensions are in mm. 2. seating plane is defined by the spherical crown of 3. not to scale. 4. ball arrangement: 14 x 14 array the solder balls. notes:- a2 top view j bottom view side view i j b n e e e1 i d d1 dimension a a1 0.85 0.75 0.60 0.40 1.0 ref. 1.00 bsc 196 15.00 bsc 15.00 bsc 1.0 ref. 12.95 12.95 13.70 13.70 min 1.35 (1.55) 0.30 max 0.50 1.75 (1.97)
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